1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an EPROM (erasable-programmable read only memory) having FAMOS (floating gate avalanche injection MOS) type cells, and a method of producing the same.
2. Description of the Related Art
Attempts are now under way to increase an integration level and miniaturize each cell of an EPROM. The miniaturization of the EPROM cell requires the miniaturizing of an isolation region. In this connection, when data is written to the EPROM cell, a writing voltage (about 12 volts) higher than that used in another memory device, such as a DRAM and SRAM, is applied to a word line (i.e., a control gate), and in this case, a conventional EPROM shown in FIGS. 1, 2 and 3 may generate a parasitic field transistor (i.e., isolation failure) between cells adjacent to each other, as indicated by a broken line arrow "a or b". Such a parasitic transistor will cause a writing failure and a reading error, and thus it is necessary to prevent a leakage of the parasitic transistor operation, to thereby ensure a normal operation of the EPROM.
Referring to FIGS. 1, 2 and 3, a conventional EPROM comprises a p-type silicon (Si) single crystalline substrate, a field insulating layer (oxide layer) 2 of SiO.sub.2, a floating gate 3, an interlaminar insulating layer (dielectric film of a capacitor) 4, a control gate 5, i.e., a word line, another interlaminar insulating layer 6, and a bit line 7. A gate insulating layer 8 lies between the Si substrate 1 and the floating gate 3, n.sup.+ -type source regions 9 and drain region 10 (in FIGS. 2 and 3) are formed in the Si substrate 1, and the bit line 7 comes into contact with the drain region 10 at a contact hole 11.
To prevent the generation of a parasitic transistor, i.e., the occurrence of a leakage current, an isolation effect of the field insulating layer must be improved, and accordingly, the following three ways of accomplishing this have been proposed. As shown in FIG. 4, the first way is to increase the thickness of the field insulating layer (A); the second way is to increase an impurity concentration of a channel cut region (p.sup.+ -type region, channel stopper) formed directly under the field insulating layer (e.g., to 5.times.10.sup.13 /cm.sup.2 from 3.times.10.sup.13 /cm.sup.2 (B); and the third way is to form an additional high concentration channel cut region (p.sup.++ -region) having an increased concentration at a center of the channel cut region (C).
Where the first way is used, when a voltage of about 12 volts is applied to the word line for writing, taking voltage margin (safety margin) into consideration, it is necessary to make the thickness of the field insulating (oxide) layer about 630 nm or more, to thereby attain a threshold voltage Vth of the parasitic transistor of 17 volts or more. When such a thick field insulating layer is formed by a thermal oxidation process, a bird's beak having a width of about 300 nm (a total of about 600 nm at both sides of one field insulating layer) is generated to prevent a reduction of the field insulating layer width (miniaturization). If the thickness of the field insulating layer is reduced, the bird's beak is diminished, but in this case, the threshold voltage of the parasitic transistor is lowered and a parasitic transistor is easily generated. If the field insulating layer is further thickened, the step coverage problem becomes serious because a surface step is made large at a later formation step of a bit line (metal wiring), with the result that such problems as wiring breakdowns and an increased wiring resistivity are increased.
With regard to the second way, i.e., increasing the dose concentration of the channel cut region as a whole, the doped impurities are undesirably diffused in a lateral direction by a heat-treatment, to thereby extend the channel cut region (impurity doped region) beyond the bird's beak. Accordingly, the channel cut region invades the device formation region 18, and therefore, the gate width is narrowed (i.e., a narrow-channel effect is caused), with the result that a threshold voltage Vth of the normal MOS transistor of the EPROM cell is varied.
With regard to the third way, i.e., forming an additional high concentration region at the center of the channel region, although the threshold voltage Vth of the parasitic transistor is sufficiently increased, the width of the isolation region (i.e., field insulating layer) is increased by the width of the high concentration region, to thus prevent a miniaturization of the device.
Futhermore, miniaturization of the EPROM is impeded. When floating gate patterning step is performed as an independent step. As shown in FIG. 5, the floating gates 3 under one (the same) control gate 5 are separated by selectively etching a conductor layer on the field insulating layer 2 by a width L. Such a floating gate 3 extends onto the field insulating layer 2, because a capacitance (C1) of the interlaminar insulating layer 4 sandwiched between the floating gate 3 and the control gate 5 becomes greater than a capacitance (C2) of the gate insulating layer 8 sandwiched between the floating gate 3 and the Si substrate 1, to thus increase the ratio of C1/C2. Such an increase of the ratio of C1/C2 raises an effective voltage between the floating gate and the Si substrate upon writing and reading, to ensure accurate writing and reading operations. Nevertheless, the extension of the floating gate 3 onto the field insulating layer 2 causes an elongation of the field insulating layer 2, which is undesirable for a miniaturization of the device. In a patterning of the floating gate, an overlapping margin (alignment allowance) of a distance D from the end of the field insulating layer 2 to the end of the floating gate 3 must be, e.g., about 0.3 .mu.m, taking an alignment accuracy of a stepper into consideration. Furthermore, an etching width L can be shortened only to the minimum patterning width (about 0.4 .mu.m), depending on an exposure and etching technique. Therefore, the field insulating layer must have a width of about 1 .mu.m, which limits any shortening (miniaturization).